1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various novel methods of forming replacement gate structures on FinFET devices and the resulting devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 that will be referenced so as to explain, at a very high level, some basic features of a traditional FinFET device. In this example, the FinFET device 10 includes three illustrative fins 14, a gate structure 16, sidewall spacers 18 and a gate hard mask 20. The gate structure 16 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device 10. The fins 14 have a three-dimensional configuration: a height 14H, a width 14W and an axial length 14L. The direction of current travel when the device 10 is operational, i.e., the gate length (GL) of the device 10, corresponds to the direction of the axial length of the fins 14. The portions of the fins 14 covered by the gate structure 16 is the channel region of the FinFET device 10. In a conventional process flow, the portions of the fins 14 that are positioned outside of the spacers 18, i.e., in the source/drain regions of the device 10, may be increased in size or even merged together (a situation not shown in FIG. 1A) by performing one or more epitaxial growth processes to form additional semiconductor material on the fins to reduce the contact resistance in the source/drain regions of the device 10.
FIGS. 1B-1E depict a typical formation process for forming fins 14 and gate structures 16 for FinFET devices. With reference to FIG. 1B, the fins 14 are typically formed by performing an etching process through a patterned hard mask layer 11 to define a plurality of trenches 13 in the substrate 12 so as to define the fins 14. A typical hard mask layer 11 is comprised of a layer of thermally grown silicon dioxide (pad oxide) formed on the substrate 12 and a layer of silicon nitride (pad nitride) formed on the pad oxide layer. The pad nitride and pad oxide layers are then patterned using photolithographic and etching techniques to thereby define the patterned hard mask layer 11. Thereafter, a layer of insulating material 22, e.g., silicon dioxide, is blanket-deposited across the substrate 12 such that it over-fills the trenches 13 and its as-deposited upper surface is positioned above the upper surface of the patterned hard mask layer 11. Then, a chemical mechanical polishing (CMP) process is performed on the layer of insulating material 22 so as to planarize its upper surface 22S with the upper surface 11S of the patterned masking layer 11 (this is the situation depicted in FIG. 1B). At this point in the process flow, the patterned masking layer 11 may be removed from above the upper surface 14S of the fins 14 by performing a selective etching process. In other process flows, the planarization process may be performed until the upper surface 22S of the insulating material is substantially planar with the upper surface 14S of the fins 14, i.e., the planarization process may be performed until such time as the patterned masking layer 11 is removed.
FIG. 1C depicts the device after several process operations were performed. First, the patterned masking layer 11 shown in FIG. 1B was removed either by etching or by performing a CMP process. Next, a recess etching process was performed on the layer of insulating material 22 such that, after the recess etching process was completed, it has a recessed upper surface 22R that is at a desired height level within the trenches 13 so as to establish the final approximate fin height for the fins 14 of the device 10. This recess etching process is sometimes referred to as a “fin-reveal” process because it reveals portions of the previously covered fins 14. Note that, in the typical prior art process flow, the layer of insulating material 22 is recessed within the trenches 13 prior to the formation of any materials for the gate structures.
FIG. 1D depicts the device 10 after several process operations were performed. First, a sacrificial gate insulation material 17, e.g., silicon dioxide, was formed across the substrate 12 and in the trenches 13 by performing a conformal deposition process. Next, a layer of sacrificial gate material 16M for the sacrificial gate, e.g., amorphous silicon, is blanket-deposited across the substrate 12 so as to over-fill the trenches 13. Due to the uneven underlying topography of the fins 14 and trenches 13, the sacrificial gate material 16M has an uneven as-deposited upper surface 16D that is simplistically depicted by the dashed line in FIG. 1D. Due to the uneven topography of the upper surface 16D, a CMP process is performed to produce a substantially planar upper surface 16S for the layer of sacrificial gate material 16M. Thereafter, a layer of gate hard cap material 20M is blanket-deposited above the planarized upper surface 16S of the layer of sacrificial gate material 16M.
FIG. 1E depicts the device 10 after the layers 20M and 16M were patterned to define a sacrificial gate structure 16 and a gate hard mask 20, and after the sidewalls spacers 18 were formed for the device 10. FIG. 1E is a cross-sectional view of the device 10 taken under the gate structure 16 and across the fins 14, wherein the recessed layer of insulating material 22 (not shown in FIG. 1A) is positioned between the fins 14. The device 10 depicted in FIG. 1E is a tri-gate (or triple gate) FinFET device. That is, during operation, a conductive region 26 (shown only on the middle fin in FIG. 1E) will be established that provides a path or channel for current to flow from the source region to the drain region. In advanced technologies, the fin width 14W (see FIG. 1A) is so small that the conductive region 26 may be comparable to the fin width 14W. The conductive region 26 forms inward of the side surfaces 14S and below the top surface 14T of the fins 14.
For many early device technology generations, the gate electrode structures of most transistor elements were comprised of a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate electrode stacks comprising alternative materials in an effort to avoid the short-channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 14-32 nm, gate structures comprised of a high-k gate insulation layer (k value of 10 or greater) and one or more metal layers, a so-called high-k dielectric/metal gate (HK/MG) configuration, have been shown to provide significantly enhanced operational characteristics over the heretofore more commonly used silicon dioxide/polysilicon (SiO/poly) configurations.
One well-known processing method that has been used for forming a transistor with a high-k/metal gate structure is the so-called “gate last” or “replacement gate” technique which is particularly effective in threshold voltage control. In the replacement gate technique, a so-called “dummy” or sacrificial gate structure (e.g., the gate structure 16 shown in FIG. 1E) is initially formed and remains in place as many process operations are performed to form the device, e.g., the formation of doped source/drain regions, performing an anneal process to activate the dopants and repair damage to the substrate caused by the ion implantation processes. At some point in the process flow after the source/drain regions are formed, the sacrificial gate structure is removed to define a gate cavity where the final HK/MG gate structure for the device is formed.
One problem encountered with traditional fabrication techniques used to manufacture FinFET devices is related to topography control. As indicated above (FIG. 1D), the as-deposited upper surface 16D of the layer of sacrificial gate material 16M is very uneven and non-planar and must be planarized before the formation of the layer of gate hard cap material 20M above the substrate 12. This is particularly problematic for extremely scaled FinFET devices, e.g., for 10 nm and beyond FinFET technologies, where the fin pitch is extremely small. The planarization process that is performed to planarize the as-deposited upper surface 16D of the layer of sacrificial gate material 16M is a timed process, i.e., the polishing does not stop on another material layer. Thus, the thickness of the sacrificial gate material layer 16M above the upper surface of the fins 14 is controlled by the duration of the polishing process. Any variation in the polishing rate and/or duration of this polishing process causes undesirable variation in the thickness of the gate material. Such variations can occur within a particular wafer, from wafer-to-wafer and/or from lot-to-lot, and can create further manufacturing problems.
Yet another problem encountered when forming FinFET devices using these prior art techniques is the lack of uniformity in the gate length (Lg) of the device 10 due to having to pattern the relatively tall (or thick) sacrificial gate material 16M in the trenches 13 between the fins 14 above the recessed layer of insulating material 22. This problem will be further described with reference to FIGS. 1F-1G. More specifically, FIG. 1F is a cross-sectional view that is taken through the long axis 14L of a fin 14 transverse to the long axis of the gate structure 16, i.e., in the current transport direction of the device, while FIG. 1G is a cross-sectional view taken through the space between the fins 14 in a direction that is substantially parallel to the gate length direction (i.e., the current transport direction) of the device 10. The upper surface 14S of the fin 14 is also depicted. As indicated in FIGS. 1F-1G, the thickness T1 of the sacrificial gate electrode material 16 above the upper surface 14S of the fin 14 is much less than the thickness T2 of the sacrificial gate electrode material 16 positioned in the trenches between the fins 14. Ideally, the gate length (Lg) of the portion of the fin 14 surrounded by the gate structure 16 will be substantially uniform and correspond to the gate length (Lg) anticipated by the design process. However, as indicated in FIG. 1G, in some cases, the sidewalls 16S of the sacrificial gate electrode material 16 may tend to flare outwardly when etched due, at least in part, to the relatively large thickness T2 of the sacrificial gate electrode material 16 in the trenches 13 between the fins 14. As a result of this flaring, the gate length (Lg) of the device near a bottom of the channel region of the device is wider than the gate length (Lg) of the device near the upper surface 14S of the fin 14. This variation in gate length can lead to problems such as slower device operation, etc. Depending on the chemistry, time and surface passivation characteristics of the sacrificial gate etch process, the opposite situation, where 16S is narrower than the gate length (Lg), may also occur. In any case, variations in uniformity of the gate length (Lg) along the fin sidewall are undesirable.
The present disclosure is directed to methods of forming replacement gate structures on FinFET devices and the resulting devices that may solve or reduce one or more of the problems identified above.